Test Pattern for input to the FPGA

[amitgangwar_vlsi]

fpga test pattern generation

hello ........

my problem is the input to the FPGA......

if my program required the 32 bit data till 32 clk cycles then
it is very time consuming process to give the input manually on each clk pulse,
and chances of error would be greater.

if we write the testbench then it is not synthesizable so we can not download it into FPGA.
is there any synthesizable testbench?????
can we download testbench on FPGA????

or is there any other method to give input to the FPGA????

many many thanks in advance
amit gangwar

 

[nxtech]

test fpga

Why not create your own test pattern generator using another FPGA as the source for the test pattern. That way you can easily modify the test pattern. Granted it is a hardware solution but it will be more representative of real life.

E

 

[avimit]

test patterns fpga

Yes, why not, you can write synthesizeable testbenches. Its really how you code them.
Look at this testbench,
http://www.vlsiip.com/vhdl/arm_bist_tb.vhd
this is mostly synthesizeable, apart from
1. initial value given to tb_counter, which you can change to putting a reset to it,
2. internally generated clock, you can change it to a clk input
3. There are no ports, but you can always, put a reset and clk port in it
Then your testbench would become synthesizeable.
It is generally recommended to write tb code whic his as far as possible synthesizeable.
Kr,
Avi
http://www.vlsiip.com

 

[amitgangwar_vlsi]

hi nxtech..
you mean to say that i have to implement a logic or hardware desogn which will generate the particular sequence which we can use as test pattern.???

thanks for reply

amit gangwar

Added after 17 seconds:

hi avimit....

you mean write a test bench simply and then give clk and reset as a port
and generate other input internally...
ok i will try it.

thanks in advance

amit gangwar

 

[rsrinivas]

Hai
just continuing the topic.
is there any way i feed data from pc and get the output to the pc to analyze the results.
I heard matlab cand do this.
can anyone shed more light on this....

 

[Iouri]

yes you can use parallel port or if you need more speed use EZ_USB from cypress