Test bench in verilog

[verilog_always]

Hi all ,
I am getting problem when ioport_signal is inout port
while writing in test bench I cannot declare it as register,,,,, What should i do to pass some value to that ioport_signal......

eg...
module eg(ioport_signal, clk)
inout ioport_signal;
input clk;
,,,,,,,,,while writing into test bench, how to pass value to inout pin....

Thanx

 

[echo47]

Try this. It drives some_value onto ioport_signal when enable_output is true:
assign ioport_signal = enable_output ? some_value : 1'bz;