test bench creation using vhdl

[blach100]

hello,

I'm trying to creaet a test bench for my program which I wrote in VHDL

all my inputs are stored in an array, so I don't have any input declared in the entity
that makes me wonder how I can change the value in my test bensh, note that in my module I have a FOR LOOP, and some IF condition,
how can I integrate it in the test bench??

thank you very much

 

[barry]

How can you not have your inputs declared in your Entity? You would get compile errors if you had no inputs.

 

[blach100]

I only have the Clock and reset as inputs

- - - Updated - - -

I only have the Clock and reset as inputs

 

[shaiko]

Post your code please

 

[TrickyDicky]

Then in your testbench you need to create a clock and reset.

 

[K-J]

hello,

I'm trying to creaet a test bench for my program which I wrote in VHDL

all my inputs are stored in an array, so I don't have any input declared in the entity
that makes me wonder how I can change the value in my test bensh, note that in my module I have a FOR LOOP, and some IF condition,
how can I integrate it in the test bench??

thank you very much

I'm assuming that you mean that the entity for the testbench has no inputs (which is correct) not that the design that you're testing has no inputs which would be non-sensical.

The way you change values in your testbench is to write code. Below is some testbench to start you off: let's assume that you the design that you're testing has a synchronous address/data bus type of interface as well as a timer that should fire at a 1 ms period.

Although it is highly unlikely that what I've described is what you're interested in testing, what you should take away from reviewing the code is the following:
- There are no input/output signals to the testbench.
- The testbench is simply more VHDL code that drives the design inputs and checks the outputs to see that they are correct
- This is an example of a self-checking testbench. What that means is that not only does it generate stimulus to the inputs to the design that you are testing, but it also automatically checks for correct functional behavior. While you will no doubt also look at waveforms, the fact that you have code that is actively monitoring the behavior of your design means that you don't have to always be checking and re-checking by looking at waveforms over and over to see that the design is still working at you debug it.
- The testbench code does not need to be synthesizable so you will see many elements in the testbench code that are not legal if you were trying to synthesize it into a physical part.
- The simulation will automatically stop due to the 'Sim_Complete' signal. Simply 'run -all' at the command prompt.

As you get used to writing testbench code, there are many other things that will come into play that can make things simpler and easier to maintain but first you need to understand the basics.

Your testbench code might look something like this (not checked for syntax, meant only to get across the idea)

entity my_testbench is 
  -- No inputs or outputs
end my_testbench;

architecture rtl of my_testbench is
   -- signals for the dut
   signal Address:     std_ulogic_vector(15 downto 0);
   signal Write_Data: std_ulogic_vector(7 downto 0);
   signal Read_Data: std_ulogic_vector(15 downto 0);
   signal Write:  std_logic;
   signal Read:   std_logic;
   signal Ack:    std_logic;
   signal Timer:  std_logic;
   signal Reset:  std_logic;
   signal Clock:  std_logic := '0';
   constant CLOCK_PERIOD := 10 ns;

   -- Testbench signals
   signal Sim_Complete:   std_logic := '0';
begin
   Clock <= not(Clock) and not(Sim_Complete) after (CLOCK_PERIOD / 2);
   Reset <= '1', '0' after 2.1 * CLOCK_PERIOD;

   MAIN : process
   begin
      Write <= '0';
      Read <= '0';
      for i in 0 to 65535 loop
         Address <= std_ulogic_vector(to_unsigned(i, Address'length));
         Write_Data <= std_ulogic_vector(to_unsigned(3*i+1, Write_Data'length));
         Write <= '1';
         wait until (Ack = '1') and rising_edge(Clock) for 10 us;
         assert (Ack = '1') and rising_edge(Clock) report "Timeout during write" severity ERROR;
         Write <= '0';
         Read <= '1';
         wait until (Ack = '1') and rising_edge(Clock) for 10 us;
         assert (Ack = '1') and rising_edge(Clock) report "Timeout during write" severity ERROR;
         assert (Read_Data = std_ulogic_vector(to_unsigned(3*i+1, Read_Data'length))
            report "Data did not read back correctly" severity ERROR;
         Read <= '0';
      end loop;
      wait;
   end process MAIN;

   TIMER_CHECKER : process
      variable Last_Rising_Edge:  time;
   begin
      wait until rising_edge(Timer);
      Last_Rising_Edge := now;
      while (Sim_Complete /= '1') loop
         wait until rising_edge(Timer);
         assert ((now - Last_Rising_Edge) > .95* 1 ms) and ((now - Last_Rising_Edge) < 1.05* 1 ms)
            report "Timer interrupt is not correct" severity ERROR;
         Last_Rising_Edge := now;
      end loop;
      wait;
   end process TIMER_CHECKER;

   DUT : entity work.my_entity port map(....); -- Instantiate the design you're testing
end rtl;

Kevin Jennings