Test bench code error in VHDL

[Arrowspace]

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
ENTITY filter_tb IS
END filter_tb;
 
ARCHITECTURE behavior OF filter_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fir_4tap
    PORT(
         Clk : IN  std_logic;
         Xin : IN  std_logic_vector(7 downto 0);
         Yout : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    
 
   --Inputs
   signal Clk : std_logic := '0';
   signal Xin : std_logic_vector(7 downto 0) := (others => '0');
 
    --Outputs
   signal Yout : std_logic_vector(15 downto 0);
 
   -- Clock period definitions
   constant Clk_period : time := 20 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: fir_4tap PORT MAP (
          Clk => Clk,
          Xin => Xin,
          Yout => Yout
        );
 
   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  
 
      wait for Clk_period*10;
 
      -- insert stimulus here 
 
      wait;
   end process;
    
      monitor : PROCESS (clk)
  variable c_str : line;
  begin
    if (clk = '1' and clk'event) then
      write(c_str,Yout);
      assert false report time'image(now) & 
        ": Current Count Value : " & c_str.all
      severity note;
      deallocate(c_str);
    end if;
  end PROCESS monitor;
 
END;

---

ERROR

ERROR:HDLCompiler:377 - "H:/Sequencial_filter/filter_tb.vhd" Line 49: Entity port xin does not match with type std_logic_vector of component port
ERROR:HDLCompiler:377 - "H:/Sequencial_filter/filter_tb.vhd" Line 50: Entity port yout does not match with type std_logic_vector of component port
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit filter_tb in library work failed

 

[Arrowspace]

I am getting an erro while outputting data in VHDL test bench

Error

ERROR:HDLCompiler:24 - "H:/Sequencial_filter/filter_tb.vhd" Line 101: write expects 2 arguments
ERROR:HDLCompiler:541 - "H:/Sequencial_filter/filter_tb.vhd" Line 101: Type void is not an array type and cannot be indexed.
ERROR:HDLCompiler:854 - "H:/Sequencial_filter/filter_tb.vhd" Line 42: Unit <behavior> ignored due to previous errors.