Test bench clock gen problem

[hithesh123]

I am generating serial clock in my test bench.
The straight forward way works fine -

                sclk <= '0';
			wait for sclk_period/2;
			sclk <= '1';
			wait for sclk_period/2;

But if I want to generate the clock, when sclk_en=1, then the test bench does not run. It just stops at the 'if' statement.

                 if (sclk_en='1') then
			sclk <= '0';
			wait for sclk_period/2;
			sclk <= '1';
			wait for sclk_period/2;
		else
			sclk<='1';		
		end if;

Not sure why it just hangs at the if statement.

 

[barry]

Hmm, I'm not sure about this. Can you post your complete process? Ordinarily, you'd have 'sclk_en' in the sensitivity list, but you can't have a sensitivity list if you're using 'wait' statements.

The way I would do this is generate a free-running clock and then use the sclk_en to enable a second process that would generate your sclk.

 

[hithesh123]

The way I would do this is generate a free-running clock and then use the sclk_en to enable a second process that would generate your sclk.

How do you do this?

Here's what I tried and it didn't work -

                   sclk_process :process
                   begin			
			sclk1 <= '0';
			wait for sclk_period/2;
			sclk1 <= '1';
			wait for sclk_period/2;		
                   end process;
	
	          sclk_en_process :process(sclk_en)
                  begin	
		     if (sclk_en='1') then
			sclk<=sclk1;
		     else
			sclk<='1';		
		     end if;
                   end process;

- - - Updated - - -

ok, got it.
Just had to add sclk and sclk1 to the process sensitivity list.

Do you do it the same way?

 

[barry]

How do you do this?

Here's what I tried and it didn't work -

                   sclk_process :process
                   begin			
			sclk1 <= '0';
			wait for sclk_period/2;
			sclk1 <= '1';
			wait for sclk_period/2;		
                   end process;
	
	          sclk_en_process :process(sclk_en)
                  begin	
		     if (sclk_en='1') then
			sclk<=sclk1;
		     else
			sclk<='1';		
		     end if;
                   end process;

- - - Updated - - -

ok, got it.
Just had to add sclk and sclk1 to the process sensitivity list.

Do you do it the same way?

I generally like to have everything synchronous, i.e., every process has a clock. What you've got will probably work fine for a testbench, but keep in mind that what you've generated is a "gated clock" which are generally avoided. This means that it is susceptible to glitches, for one thing.

 

[TrickyDicky]

I generally like to have everything synchronous, i.e., every process has a clock. What you've got will probably work fine for a testbench, but keep in mind that what you've generated is a "gated clock" which are generally avoided. This means that it is susceptible to glitches, for one thing.

If its a testbench, it wont cause glitches. Its just a clock. But you have to bare in mind that with this code, sclk is 1 delta behind sclk1. This may cause some odd things to appear to happen, depending on where you have used sclk and sclk1.

for example here:

process(sclk1)
begin
  if rising_edge(sclk1) then
    some_en <= not some_en;
  end if;
end process;

process(sclk)
begin
  if rising_edge(sclk) then
    if some_en = '1' then
      --do something
      --When you look at the waveform, it may look like something happens when some_en = '0'
    end if;
  end if;
end process;

this is because, by the time sclk is actually rising, some_en has already changed, and so the thing will appear to happen on the rising edge of the enable, because of the extra delta delay caused by the signal transfer of sclk1 to sclk.

This is just going to happen in simulation. In the real hardware it would just be a gated clock.