Tessent scan insertion library

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aria62

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Hi.

I have created a gate-level netlist from my design using Synopsys DC. Now I am trying to do the scan insertion in the Tessent shell. I assume that after reading the Verilog netlist, Tessent needs to read a library file with the .lib extension. From an example, I noticed that this library is something like Spice library that contains some models of flip-flops and logic gates. Does anybody know how this library can be obtained? Should I create some libraries manually for the scan insertion?
Having said that I have used freepdk45 for creating the gate-level netlist and it doesn't contain any lib file for scan insertion.

Thanks
 

The scan ffs are available in standard library kits (.db/.lib). If you want a scan chain, then this has to be enabled during the synthesis in DC. Synthesizer will pick scan ffs from the provided library for that. Std cell libraries in .db/.lib format have the timing power/delay information in tabulated format.
 
Thank you Ranaya. The format of the .lib file available in freepdk45 library is different from the .lib needed in Tessent. To solve the problem, I converted the available stdcells.v file to a model library using libcopm and then I modified it manually to obtain such a definition:

Code: 
model NAND2_X1(A1, A2, ZN) (
  cell_type = NAND;
  input(A1, A2) ()
  output(ZN) (primitive = _nand(A1, A2, YZN)
)

while the definition in stdcells.lib in freepdk is like:

/******************************************************************************************
   Module           : NAND2_X1
   Cell Description : Combinational cell (NAND2_X1) with drive strength X1
  *******************************************************************************************/
  cell (NAND2_X1) {
    drive_strength      : 1;
    area                : 0.798000;
    pg_pin(VDD) {
        voltage_name : VDD;
        pg_type      : primary_power;
    }
    pg_pin(VSS) {
        voltage_name : VSS;
        pg_type      : primary_ground;
    }

    cell_leakage_power  : 17.393360;
    leakage_power () {
        when           : "!A1 & !A2";
        value          : 3.482556;
    }
    leakage_power () {
        when           : "!A1 & A2";
        value          : 24.799456;
    }
    leakage_power () {
        when           : "A1 & !A2";
        value          : 4.085038;
    }
    leakage_power () {
        when           : "A1 & A2";
        value          : 37.206389;
    }
    pin (A1) {
        direction       : input;
        related_power_pin       : "VDD";
        related_ground_pin      : "VSS";
        capacitance     : 1.599032;
        fall_capacitance    : 1.529196;
        rise_capacitance    : 1.599032;
    }
    pin (A2) {
        direction       : input;
        related_power_pin       : "VDD";
        related_ground_pin      : "VSS";
        capacitance     : 1.664199;
        fall_capacitance    : 1.502278;
        rise_capacitance    : 1.664199;
    }
    pin (ZN) {
        direction       : output;
        related_power_pin   : "VDD";
        related_ground_pin  : "VSS";
        max_capacitance     : 59.356700;
        function        : "!(A1 & A2)";
.
.
.
 
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aria62

That is the right approach to convert stdcells.v file to a model library using libcopm. Hence you are provided with libcomp from Siemens/mentor.
 

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