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[SOLVED] Terasic ADDA

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jayeffe

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Hello everyone. I apologize in advance because I don't speak English well but I try to make myself understood. I am carrying out an educational project which consists in the use of the ADDA card.

In practice, the starting point that has been suggested to me is the use of the "ADA demostration". Here the oscillator waveform is generated, summed.
In addition to this I have to create a loop that connects the digital output to the input of the dac.

Then I have to filter through fir filter.
Immagine 2022-01-08 180925.png


Immagine 2022-01-22 203024.png


Immagine 2022-01-08 182427rr.png


I have attached the netlist of the example project.
For filtering, I read from the internet that it is placed by taking the ADC_DA signal as input

The problem I'm having with quartus is to use the signal tap.


in the photo there are the signals that are part of the example project. If I add other signals, which are part of the project (for example ADC_DA) the signal tap tells me to recompile or gives me other errors.

thanks everyone for the help
 

If I add other signals, which are part of the project (for example ADC_DA) the signal tap tells me to recompile or gives me other errors.
Yes, need for recompilation after signaltap change is normal operation, not an error. What are the other problems?
 

often goes out program the device to continue. other times invalid jtag

initially I compile the project with the sof file present in the form that refers to the example. Then I added the ADC_DA signal, saved the signal tap and recompiled. I don't understand where the mistake lies. Maybe in the .sof file that is generated.


View attachment 174052
 

here the image
 

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  • Immagine 2022-01-08 180925.png
    Immagine 2022-01-08 180925.png
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  • Immagine 2022-01-08 182427rr.png
    Immagine 2022-01-08 182427rr.png
    52.6 KB · Views: 174
  • Immagine 2022-01-22 203024.png
    Immagine 2022-01-22 203024.png
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