Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Terasic ADDA

Status
Not open for further replies.

jayeffe

Junior Member level 2
Joined
Jan 22, 2022
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
117
Hello everyone. I apologize in advance because I don't speak English well but I try to make myself understood. I am carrying out an educational project which consists in the use of the ADDA card.

In practice, the starting point that has been suggested to me is the use of the "ADA demostration". Here the oscillator waveform is generated, summed.
In addition to this I have to create a loop that connects the digital output to the input of the dac.

Then I have to filter through fir filter.
Immagine 2022-01-08 180925.png


Immagine 2022-01-22 203024.png


Immagine 2022-01-08 182427rr.png


I have attached the netlist of the example project.
For filtering, I read from the internet that it is placed by taking the ADC_DA signal as input

The problem I'm having with quartus is to use the signal tap.


in the photo there are the signals that are part of the example project. If I add other signals, which are part of the project (for example ADC_DA) the signal tap tells me to recompile or gives me other errors.

thanks everyone for the help
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,894
Helped
14,482
Reputation
29,234
Reaction score
13,391
Trophy points
1,393
Location
Bochum, Germany
Activity points
286,515
If I add other signals, which are part of the project (for example ADC_DA) the signal tap tells me to recompile or gives me other errors.
Yes, need for recompilation after signaltap change is normal operation, not an error. What are the other problems?
 

jayeffe

Junior Member level 2
Joined
Jan 22, 2022
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
117
often goes out program the device to continue. other times invalid jtag

initially I compile the project with the sof file present in the form that refers to the example. Then I added the ADC_DA signal, saved the signal tap and recompiled. I don't understand where the mistake lies. Maybe in the .sof file that is generated.


View attachment 174052
 

jayeffe

Junior Member level 2
Joined
Jan 22, 2022
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
117
here the image
 

Attachments

  • Immagine 2022-01-08 180925.png
    Immagine 2022-01-08 180925.png
    29.8 KB · Views: 38
  • Immagine 2022-01-08 182427rr.png
    Immagine 2022-01-08 182427rr.png
    52.6 KB · Views: 35
  • Immagine 2022-01-22 203024.png
    Immagine 2022-01-22 203024.png
    359.7 KB · Views: 36

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top