tell the mistake in the verilog code

[Pulkit Varshney]

it's not the full code it's just a part of it. h[p] is number ranging from 0 to 3. My problem is that when i-p<0 than the code within if statement is not executing and i am getting result only when i-p>0. Please, tell me where i am making the mistake?
for(i=0;i<4;i=i+1)
begin

y=0;
for(p=0;p<4;p=p+1)
begin

for(j=0;j<h[p];j=j+1)
if((i-p)<0)
y=y+k[p-i];
else
y=y+k[i-p];
end

o0=y[0];o1=y[1];o2=y[2];o3=y[3];
end

end

 

[guitarguy12387]

I suspect the real problem is you seem to be treating verilog like a software language instead of an HDL

 

[vlsi_whiz]

Yup, thats the problem here.. the for-loop will not work in synthesis or even simulation for that matter. I dont think verilog supports this kind of array calculations.

 

[FvM]

A for loop will generally work in synthesis and simulation. You have to consider however, that it does not implement a sequence in time. All calculations are performed in a single clock cycle.

I suspect the real problem is you seem to be treating verilog like a software language instead of an HDL

It looks like. But this doesn't necessarily mean, that the code isn't synthesizable.

As written, the code doesn't make much sense. There's e.g. an unpaired end and the assignment of output values seems misplaced. One prerequirement for the loop construct to be synthesizable is, that h[p] must be an array of constants, I think.