tell me why please? Simulation gives wrong output

tell me why please?

hi ppl
i have this example and it is correct but i could'nt get simlation the result tell me 16'UUUU
why?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity mmmmm is
Port ( clk : in STD_LOGIC;
-- i:in integer:=1;
result : out STD_LOGIC_vector(15 downto 0);
m : in STD_LOGIC_vector(7 downto 0);
n : in STD_LOGIC_vector(7 downto 0);
start:in std_logic);

end mmmmm;

architecture Behavioral of mmmmm is
signal count:integer:= 0;
signal n1,m1:std_logic_vector(7 downto 0);
signal result1:std_logic_vector(15 downto 0);
begin
process(clk)

begin

if (rising_edge(clk))then
if( start = '1' )then
result<="0000000000000000";
result1<="0000000000000000";
count <=0;
m1<=m;
n1<=n;

else
if (count /= 8 )then
if (m1(0)='1')then
result1<=result1+n1;
end if ;
n1 <=n1(6 downto 0) & '0';
m1 <='0'& m1 (7 downto 1);
count <=count+1;
end if ;
end if;
end if ;
result<=result1;

end process ;

end Behavioral;

Re: tell me why please?

Hi,

My result is not 16'UUUU

Check that m and n have been initialized (not U or X) and that you use your reset signal 'start'. Assuming you have a clock signal.

Devas

Re: tell me why please?

they are not u or x ...i entered it as unsigend no.
please can you send me a capture of simulation of your result and also the report of synthesis of it i need it now ...it is not runing here

sorry i want to say here
ppl want to know why it give me just one result if i input more than value to n and m it don;t give me just the first input