technology TSMC with N-WELL and P-WELL in the same substrate

[fasto2008]

HELLO,

I'm so sorry for my english writing but i'm happy to listen to you.
The TSMC fabrication processes available through MOSIS(provides access to fabrication of prototype)
include 0.35 µm CMOS, 0.25 µm CMOS, 0.18 µm CMOS, and 0.13 µm CMOS.

I select:
TSMC 0.18 µm
process: CR018(CM018)
description:Mixed-mode/RF,RPO,MiM

I find many parameters https://www.mosis.com/Technical/Testdata/tsmc-018-prm.html)

T77A_MM_NON_EPI_THK-MTL_HR8
T77A_MM_NON_EPI_THK-MTL
T77A_MM_NON_EPI
T73D_MM_NON_EPI
T73D_MM_NON_EPI_THK-MTL
T6CA_MM_NON_EPI_THK-MTL_HR8
T6CA_MM_NON_EPI_THK-MTL
T6CA_MM_NON_EPI
T68B_MM_NON_EPI
T68B_MM_NON_EPI_THK-MTL
T66D_MM_NON_EPI_THK-MTL
T66D_MM_NON_EPI
T64H_MM_NON_EPI_THK-MTL
T64H_MM_NON_EPI
T64H_LO_EPI
T58F_MM_NON_EPI_THK-MTL
T58F_MM_NON_EPI
T58F_LO_EPI
T57Q_MM_NON_EPI_THK-MTL
T57Q_MM_NON_EPI
T57Q_LO_EPI
T55U_MM_NON_EPI
T55U_MM_NON_EPI_THK-MTL
T55U_LO_EPI
T53R_MM_NON_EPI_THK-MTL
T53R_MM_NON_EPI
T53R_LO_EPI
T4BK_MM_NON_EPI_THK-MTL
T4BK_LO_EPI
T4BK_MM_NON_EPI
T49P_LO_EPI
T49P_MM_NON_EPI_THK-MTL
T49P_MM_NON_EPI
T47R_MM_NON_EPI_THK-MTL
T47R_MM_NON_EPI
T46U_MM_NON_EPI_THK-MTL
T46U_MM_NON_EPI
T46U_LO_EPI
T44E_MM_NON_EPI
T44E_MM_NON_EPI_THK-MTL
T44E_LO_EPI
T42P_MM_NON_EPI_THK-MTL
T42P_MM_NON_EPI
T42P_LO_EPI
T3CV_MM_NON_EPI
T3CV_LO_EPI
T3CV_MM_NON_EPI_THK-MTL
T3AZ_MM_NON_EPI_THK-MTL
T3AZ_MM_NON_EPI
T3AZ_LO_EPI
T38N_MM_NON_EPI
T38N_MM_NON_EPI_THK-MTL
T38N_LO_EPI
T36Q_MM_NON_EPI
T36Q_MM_NON_EPI_THK-MTL
T36Q_LO_EPI
T34B_MM_NON_EPI
T34B_MM_NON_EPI_THK-MTL
T34B_LO_EPI
T32L_MM_NON_EPI
T32L_MM_NON_EPI_THK-MTL
T2CU_MM_NON_EPI_THK-MTL
T2CU_MM_NON_EPI
T2CU_LO_EPI
T29B_MM_NON_EPI
T29B_MM_NON_EPI_THK-MTL
T29B_LO_EPI
T28M_MM_NON_EPI_THK-MTL
T28M_LO_EPI
T28M_MM_NON_EPI
T26X_LO_EPI
T26X_MM_NON_EPI_THK-MTL
T26X_MM_NON_EPI
T24I_MM_NON_EPI_THK-MTL
T24I_MM_NON_EPI
T24I_LO_EPI
T22T_MM_NON_EPI
T22T_MM_NON_EPI_THK-MTL
T22T_LO_EPI
T1CH_MM_NON_EPI_THK-MTL
T1CH_MM_NON_EPI
T1CH_LO_EPI
T1AX_MM_NON_EPI_THK-MTL
T1AX_MM_NON_EPI
T1AX_LO_EPI
T18H_LO_EPI
T18H_MM_NON_EPI
T18H_MM_NON_EPI_THK-MTL
T16X_LO_EPI
T16X_MM_NON_EPI
T16X_MM_NON_EPI_THK-MTL
T15J_MM_NON_EPI
T15J_LO_EPI
T14B_LO_EPI
T14B_MM_NON_EPI
T12K_MM_EPI
T12K_LO_EPI
T11B_LO
T11B_MM

EPI = Epitaxial wafers
NON_EPI = Non-epitaxial wafers
LO = Logic process
MM = Mixed-mode process
THK-MTL = Thick metal option (MM only)

The goal is to have N-well and p-well in the same substrate.
The problem is, when i get to all of them i don't find p-well parameters.

Thank you for your help.

 

[drabos]

okay, so as I understand you have epitaxial layers as wells...In this case the p well is there, where there is no n-well...
Most of the cases that is the case...

So again, the substrate (p type) and there is an epitaxial p-well and an epitaxial n-well on the substrate

If you have a triple well process, then you have n-well and p-well layer descriptions, in this case you could use different bulk voltages for p-wells