Techniques to remove setup violations in a critical path

[s0shinde]

Hello,
I have a critical path in my design. The combinatorial logic between two flipflops can not be reduced further to remove setup violations. Any suggestions on this?

 

[eda_wiz]

Increase Drive strength of the combinational gates to reduce the delay.

introduce slight skew between successive flops to increase the clock freq(may be done by introducing some buffers in the clock)

Try RETIMING.. tell your tool to do this

Use a better process library

 

[s0shinde]

hello whizkid,
I had tried inserting pipelines and flattening the hierarchical design. Also I did uniquify. But it still doesn't meet the timing. My employer doesn't want me to reduce the clock frequency and inserting skew in the clock in between critical path won't insert skew in clock in the next stages, but I will have to modify the timing in next stages accordingly. I gave this idea but the design manager doesn't agree. Any other suggestion.

 

[linuxluo]

hi,
first ,using compile_ultra in DC. then using PC to see if violation is exist or not.
if the violation is just exceed constraint no more than 5%, just do p&r .using route tool to resolve this violation.
and you can try rtl compile from cadence to try and this tool is very expensive.

 

[rakko]

if none of these methods work then you might have to design the offending block using custom logic. I have seen improvement of up to 30% between standard logic and custom logic.

 

[zyphor]

it depends which stage are you in.

if you are in synthesis stage. you can orginize you code, or change synthesis strategy.

if you are in APR stage, you can select the cell 's transition is big and increase its size to diminish the delay.

 

[eexuke]

Hi,
I think it needs manual ECOs.You can try as following:
1)check the placement in your layout,place the related logic cells as near as you can
2)check the routing,you can use double-width routing to reduce some net delay
3)manual logic resynthesis,such as combine two INV to one BUF
4)Early & Late clock are efficient ways,but the skew......

 

[linli]

customer logic/cell is a good solution for this kind of issue.

 

[sandusty]

Hi, s0shinde:

Which phase are you in your design? You might want to use:

Buffer sizing
Buffer insertion
Bring critical signal close to the sink,
Circuit replication (if that's a placement problem)
Logic re-write (mentioned in the eexuke's ECO above)
Wire sizing (near the source, otherwise increase R, C at the same time, you wouldn't get a better results)
Cut fanouts and build a tree
Re-layout some of the wires to the low r/c layers
Move clock edge, ...

Of coures, change technology, fundry, cell lib, pipe, block partition, archecture and spec will be very helpful...

 

[sandusty]

BTW, do you want to change to latch-base design and using cycling stealing?