Technical Verilog Design Questions

[projectx100]

Howdy all,

1. Can I use a genvar value for a comparison with vector bit signal rather than just accessing the specific bit in a vector.
Example: vector_sig == j
where j is a genvar and vector_sig is wire [10:0].
If not, how can I generate multiple blocks and still have a reference to the index value of the block I created.

Code example:

genvar j;
generate
for (j=0;j<SRC_DEST_PAIR_NUM;j=j+1)
begin: conversion
assign net_addr_to_counter_id_val[j] = j;
assign net_addr_to_counter_id_ns[j] = (prediction_result_src_dest ==  net_addr_to_counter_id_val[j]) ? first_free_counter_id : net_addr_to_counter_id[j];
registerN #(LG_NUM_PREDICTIONS, 'd0) counter_id_ff(
	.clk(clk),
	.reset(reset),
	.en(),
	.ns(net_addr_to_counter_id_ns[j]),
	.ps(net_addr_to_counter_id[j])
	);
end
endgenerate

2. Can I declare and assign a signal in the same line?
Example: wire my_sig = a & b;

Thanks in advance,

Nad.

 

[jrwebsterco]

I've been able to do something similar to what you ask in (1), though I did get warnings about e.g. truncation issues due to the genvar being 32-bit (integer).
But, why ask instead of trying this out for yourself in a simulator - have you and did you encounter problems?
(note that this generate stuff was introduced in Verilog-2K, and any EDA tool would need to be modern enough to support that)

For (2), this is legal, and also clearly described as such in Verilog language refs (which are readily available on the web).