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TCP/IP or UDP with Xilinx Virtex2Pro

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hanstarro

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xilnet

Hi,

does anybody have experience with UDP(TCP/IP) stacks available for Virtex2Pro FPGA? Is the XilNet solution available in EDK a good solution?

Are there any reference designs out there incorporating a
Ethernet MAC (EMACLite, EMAC or Opencore EthMac?) and
a UDP stack?

And how the ... do i get those encrypted Xilinx IP Cores to compile in Modelsim?

thanks in advance!

-h
 

does anybody have experience with UDP(TCP/IP) stacks available for Virtex2Pro FPGA? Is the XilNet solution available in EDK a good solution?

Are there any reference designs out there incorporating a
Ethernet MAC (EMACLite, EMAC or Opencore EthMac?) and
a UDP stack?

And how the ... do i get those encrypted Xilinx IP Cores to compile in Modelsim?

thanks in advance!

-h
 

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