TCL tutorial or example to write testbench for VHDL code

[cwjcwjcwj]

testbench tcl

I am beginner of using TCL to write testbench for my VHDL code. Anyone have a good tutorial or example that i can start with? thank you very much.

 

[cachep]

fpga testbench tcl

You can see h**p://www.altera.com/support/examples/tcl/counter_tcl.html or www.model.com/support/technotes/tcl_tk/tcl_testbench.pdf

 

[aiko89]

Re: fpga testbench tcl

module count (clk, rst, enable, cnt);

input clk, rst, enable;
output [3:0] cnt;

reg [3:0] cnt;

always @(posedge clk or posedge rst) // async active high reset
begin
if(rst)
cnt <= 0;
else if(enable)
cnt <= cnt + 1;
end

endmodule

============================================================

do you know how to use this wan to do a testbench?

 

[vaisram]

hi aiko89.. if you want to know how to write a testbench for any given code then check out
WWW.TESTBENCH.IN website.. Here they talk about all verification concepts in detail and sample programs to help you out..