Tapeout chip with few of worst corner checked? Is it safe?

[huckle]

What are the reasons behind running the signoff at so many corners in today's chips. Why we can't tapeout the chip with running a few worst corners? like pick up the best/worst for Process, voltage, and temperature each, and run signoff test at all possible combination of all these. (2 x 2 x 2) = 8 corners.

Interview question. How should this be answered?

 

[ThisIsNotSam]

because what you think is worst corner is not worst. there are weird things in modern technologies, like temperature inversion. it's better to let the tool crunch on all corners than to ruin a tapeout because you saved some CPU cycles.

 

[huckle]

temperature inversion is already accounted for in the question I believe, since they are saying pick up best and worst values for Temperature (two values).

What other will impact timing other than P,V,T? Is it parasitic corners that are missing, which makes number or corners go up? Or possibly OCV effect? Anyone have more clarity on whether its one or both of above? Kindly elaborate.

Thanks

 

[dick_freebird]

What is "best" and "worst" depends on the circuit and
the expectations for it. What is best for digital prop
delay is not best for an on-chip ADC or op amp.
The higher the mix of functions beyond plain digital,
the less appropriate "corners" are as a design
vetting method. The same corner that made your
digital section fast, could make your op amp slow
(thin ox capacitance).

With modern CMOS flows offering anywhere from
2 to 4 VT implant options, times two unrelated
oxide thicknesses and barely-lithography-capable
length and width control (which come from two
separate etches) there's a lot of ground to cover.

A complementary question is, "what happens if you
are wrong about spec compliance?".

If it's a science project and the science can stand
if you're a bit off on any parametric performance
line item, maybe you just run FFFFFFF and SSSSSS
and beg for waivers.

If you can show functionality regardless and only
a few spec "breakouts" then maybe you want the
silicon in order to say whether it's you or the foundry
PDK that's making problems where maybe there
are none (or maybe not). Blind trust in corner models
is never deserved, they are always gamed to make
everything shippable and make the fab look good,
regardless of the pain at the customer end.

If it's a contractual product design and there's legal
consequences for anything other than 100.00% first
pass success, defined by both functionality and
detailed spec compliance in all things, you'd best
do your due design diligence.

 

[ThisIsNotSam]

temperature inversion is already accounted for in the question I believe, since they are saying pick up best and worst values for Temperature (two values).

What other will impact timing other than P,V,T? Is it parasitic corners that are missing, which makes number or corners go up? Or possibly OCV effect? Anyone have more clarity on whether its one or both of above? Kindly elaborate.

Thanks

yes, interconnect corners also matter. OCV is applied as a derate factor, it does not become a corner per se.

in summary, you have PVT corners for transistors, corners for the interconnect, and functional corners. it's usual to have 4+ for the first, 4+ for the second, 10+ for the latter. it's not hard to reach 80 scenarios for a large SoC. and that is fine, the tools don't do the same work 80 times. they understand some corners dominate others and will ignore a lot of them during design implementation phases.

--- Updated Aug 12, 2020 ---

If you can show functionality regardless and only
a few spec "breakouts" then maybe you want the
silicon in order to say whether it's you or the foundry
PDK that's making problems where maybe there
are none (or maybe not). Blind trust in corner models
is never deserved, they are always gamed to make
everything shippable and make the fab look good,
regardless of the pain at the customer end.

this changes from foundry to foundry in my experience. TSMC for instance is super conservative in their corners, you never see those numbers in real silicon. not even in MC simulations you can reproduce some bad numbers they give you.

 

[huckle]

yes, interconnect corners also matter. OCV is applied as a derate factor, it does not become a corner per se.

in summary, you have PVT corners for transistors, corners for the interconnect, and functional corners. it's usual to have 4+ for the first, 4+ for the second, 10+ for the latter. it's not hard to reach 80 scenarios for a large SoC. and that is fine, the tools don't do the same work 80 times. they understand some corners dominate others and will ignore a lot of them during design implementation phases.

Hi, Could you please give some examples of functional corners? I understand transistor PVTs are : SS, FF, SF, FS and TT. Interconnect corners: C-worst, RC-worst, C-best, RC-best.

 

[ThisIsNotSam]

say you have a scan mode at freq1, you have a shut-off island at mode2, you have a dynamic clock frequency with 4 possible values. those all become design corners or functional corners. you still have to close timing for all cases.