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Taking care of retiming during LEC

fragnen

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How retiming that exist in a gate level HDL but not in the corresponding RTL can be taken care during LEC?
 

wizard

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For formality, most optimization including retiming are stored in svf file that you need not much extra user input. For Conformal, there are some commands like 'analyze retiming' for retimed modules.
 

ThisIsNotSam

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retiming engines can annotate the design to track the changes they did. it's not rocket science. a simple svf file does the trick.
 

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