tablet counter system design

[funjoke]

tablet counter system verilog

i need to do a 2 digit bcd counter testbench verilog ,here i attached the verilog but i dunno correct a not

 

[nandhu015]

bcd countrer for tablet counter system

i need to do a 2 digit bcd counter testbench verilog ,here i attached the verilog but i dunno correct a not

Where is the attachment

Nandhu

 

[karper1986]

counter design

Hi funjoke,

Here is some code of BCD counter. Hope it helps you.

Best regards,
Karper.

 

[funjoke]

tablet counter system

i have attached the testbench 2 digit bcd counter here .those who know it pls help me thanks


module tb_2digit_bcd_counter
#(parameter TB_CNTR_SIZE=3)
();

//***************************************

//output declaration
wire[3:0] tb_w_op_bcd_tens_digit;
wire[3:0] tb_w_op_bcd_units_digit;

//input declaration
reg tb_r_ip_bcd_start_bottling;
reg tb_r_ip_bcd_tablet_in;
reg tb_r_ip_bcd_bottle_in;
reg tb_r_ip_bcd_bottle_full;
reg tb_r_ip_bcd_sys_reset;
reg tb_r_ip_bcd_sys_clk;

//****************************************

//Module instantation

counter
test_counter
(.op_bcd_tens_digit(tb_w_op_bcd_tens_digit),
.op_bcd_units_digit(tb_w_op_bcd_units_digit),
.ip_bcd_tablet_in(tb_r_ip_bcd_tablet_in),
.ip_bcd_bottle_in(tb_r_ip_bcd_bottle_in),
.ip_bcd_start_bottling(tb_r_ip_bcd_start_bottling),
.ip_bcd_ip_sys_clock(tb_r_ip_bcd_sys_clk),
.ip_bcd_ip_sys_reset(tb_r_ip_bcd_sys_reset));



//******************************************

//Clock waveform generation.
initial tb_r_ip_bcd_sys_clk<=1;
always#10 tb_r_ip_bcd_sys_clk= ~tb_r_ip_bcd_sys_clk;

//Signals initialization
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
initial begin
tb_r_ip_bcd_sys_reset=1'b1;
tb_r_ip_bcd_bottle_in=1'b0;
tb_r_ip_bcd_tablet_in=1'b0;
#20 tb_r_ip_bcd_sys_reset=1'b0;
tb_r_ip_bcd_bottle_in=1'b1;

//******************************************

//Test case 1:Start bottling
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_start_bottling)
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<=0000;
else
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<={tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit};

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

//Test case 2:Count first tablet

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_tablet_in==1)
tb_w_op_bcd_units_digit<=0001;tb_w_op_bcd_tens_digit<=0000;
else
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<={tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit};

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

//Test case 3:second tablet drop detected

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_tablet_in==2)
tb_w_op_bcd_units_digit<=0010;tb_w_op_bcd_tens_digit<=0000;
else
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<={tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit};

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

//Test case 4:Test ten didit

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_tablet_in==10)
tb_w_op_bcd_units_digit<=0000;tb_w_op_bcd_tens_digit<=0001;
else
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<={tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit};

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

//Test case 5:Bottle full(99 tablet)counting suspended

@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_bottle_full)
tb_w_op_bcd_units_digit<=1001;tb_w_op_bcd_tens_digit<=1001;
else
tb_w_op_bcd_units_digit<=tb_w_op_bcd_units_digit+1'b1;

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

//Test case 6:When bottle in is asserted counter reset to 00

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_bottle_full&&tb_r_ip_bcd_bottle_in)
tb_w_op_bcd_units_digit<=0000;tb_w_op_bcd_tens_digit<=0000;
else
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<={tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit};

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

//Test case 7:System reset

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

@(posedge tb_r_ip_bcd_sys_clk)
if(tb_r_ip_bcd_sys_reset)
tb_w_op_bcd_units_digit<=0000;tb_w_op_bcd_tens_digit<=0000;
else
{tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit}<={tb_w_op_bcd_units_digit,tb_w_op_bcd_tens_digit};

repeat(20)@(posedge tb_r_ip_bcd_sys_clk)
$stop;

end

endmodule