systemverilog 3.1 design subset
Accellera pushes for 'unified assertions' (Dec. 6, 2002)
The Accellera standards organization is going to unify several assertions
that can be used across a variety of tools.
Accellera bills as the industry's first
hardware design and verification language (HDVL).
Unified assertions will link
1) Accellera's Property Specification Language (PSL),
2) SystemVerilog 3.1 and
3) Open Verification Library (OVL).
As "the first HDVL," it will "combine
1) powerful assertions,
2) testbench creation,
3) a direct C interface and
4) high- level abstraction.
The current SystemVerilog 3.0 has assertions derived from
1) the Superlog language, and
2) Synopsys' Open Vera Assertions (OVA).
The unified assertions, he said, will serve as the kernel of PSL.
The assertion capability in SystemVerilog 3.1 will be much more complete than what's in 3.0, such as
1) concurrent assertions,
2) dynamic variable construct for concurrent evaluation and
3) "assertion template" that can be used to construct libraries.
The testbench language in SystemVerilog 3.1 will provide features for
1) stimulus generation,
2) checkers,
3) abstract modeling and
4) structured connection to multiple interfaces.