SystemVerilog: wire (inout) inside interface not updated?

[legendbb]

I was attempting to use inout port inside interface with task in manipulating the inout signal.

But I can only get inout signal to update correctly, only if it's included inside port list of the interface.

ioSig updates correctly when task is called:

interface my_if(inout wire ioSig)
assign ioSig = (sigEn == 1'b0) ? 1'b1 : 1'0;
...
task my_task;
...
begin
#10ns
sigEn = 1'b0;
...

ioSig fails to update:

interface my_if(...)
wire sigEn;
assign ioSig = (sigEn == 1'b0) ? 1'b1 : 1'0;
...
task my_task;
...
begin
#10ns
sigEn = 1'b0; // I've single step over here, no update on assign statement
...

What am I missing?

Thanks for any comments,

:?:

 

[dave_59]

A couple of problems

You are not allowed to make procedural assignments to wires. You are making one to sigEn. You should have gotten a compiler error. Maybe this was a typo when you copied it.

A continuous assignment needs time for updates on the RHS to propagate to the LHS. If you are single stepping, you may need to advance time far enough to see the change.

 

[legendbb]

A couple of problems

You are not allowed to make procedural assignments to wires. You are making one to sigEn. You should have gotten a compiler error. Maybe this was a typo when you copied it.

A continuous assignment needs time for updates on the RHS to propagate to the LHS. If you are single stepping, you may need to advance time far enough to see the change.

Thanks Dave,

I don't think it didn't have enough time to update, since the simulation never got the updated signal value.

The procedural assignment is side my task().