systemVerilog verification

[choonlle]

I'm writing my code in verilog 2001. Can i use systemVerilog in test bench coding to verify my RTL code in verilog 2001?


Thanks.

 

[aji_vlsi]

I'm writing my code in verilog 2001. Can i use systemVerilog in test bench coding to verify my RTL code in verilog 2001?


Thanks.

Ofcourse you can, we show several examples in our SNUG papers, books etc. See www.noveldv.com or www.systemverilog.us for detials

Ajeetha, CVC
www.noveldv.com

 

[salma ali bakr]

yah
systemverilog can be used for assertions, test bench generation and even in design

 

[choonlle]

What is assertion??!! can you explain more about that.

 

[salma ali bakr]

do u know the keyword "assert" in VHDL
it is just a way to tell u if a certain condition happened or not
or in other words, a certain property in your design is occuring or not

for instance if u say in VHDL:

assert (clear /= '1')
report "clear is set!"
severity warning;

this means that u want to make an assertion on the value of clear
if clear is '1' then the assertion is false and a report or a message will be written to indicate that: "clear is set!"
and that the level of severness of this condition is a warning
if clear isn't '1' then nothing will happen

or in PSL for instance:

assert always (A and B)

this means that u always want to check if A and B are True at the same time
if this doesn't happen then your assertion or your property is false

i hope that was clear
and don't hesitate to ask more

 

[darylz]

you can find more discussion on this at https://verificationguild.com/