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SystemVerilog simulation in Questasim 6.2b ?

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subos

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questasim 6.2b systemverilog

The following warning is reported.

Some checking for conflicts with continuous assignments to variables not yet supported. Run vopt to provide additional design-level checks.

It can be seen clearly in the technotes that QuestaSim6.2b supports "continuous assignments to variables". Why does it report the above warning?
 

walid farid

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systemverilog svchk

Hi,
Can you send the file which gives you this warning .. ?
 

subos

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[svchk] - some checking for conflicts

walid said:
Hi,
Can you send the file which gives you this warning .. ?

Thanks for your reply.

The following is the source file. I download it from an open-core website.

/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Pipelined channel (link) between routers
*
* 'stages' may range from 0 (routers are clocked but link is simply a wire)
* to N
*
*/

module NW_pipelined_channel (data_in, data_out, clk, rst_n);

parameter type reg_t = flit_t;

parameter stages = 4;

input reg_t data_in;
output reg_t data_out;
input clk, rst_n;

genvar st;

reg_t ch_reg[stages-1:0];

generate
if (stages==0) begin
// no registers in channel
assign data_out = data_in;
end else begin
for (st=0; st<stages; st++) begin:eachstage
if (st==0) begin
// first register in channel
NW_reg #(.reg_t(flit_t)) rg (.data_in(data_in), .data_out(ch_reg[0]), .clk, .rst_n);
end else begin
// other registers
NW_reg #(.reg_t(flit_t)) rg (.data_in(ch_reg[st-1]), .data_out(ch_reg[st]), .clk, .rst_n);
end
end

assign data_out = ch_reg[stages-1];

end
endgenerate


endmodule // NW_pipelined_channel

The related warnings are shown below:
# ** Warning: lib/NW_pipelined_channel.v(31): [SVCHK] - Some checking for conflicts with continuous assignments to variables not yet supported. Run vopt to provide additional design-level checks.
# ** Warning: lib/NW_pipelined_channel.v(43): [SVCHK] - Some checking for conflicts with continuous assignments to variables not yet supported. Run vopt to provide additional design-level checks.
 

walid farid

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these features are only supported in questasim.

What i figured that you get this message only if the continuous assignments are inside a generate block.
However, when i ran a simulation the results were ok.
 

    subos

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subos

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systemverilog questasim

walid said:
What i figured that you get this message only if the continuous assignments are inside a generate block.
However, when i ran a simulation the results were ok.

Thanks for your help.

So, I can omit these warnings.
 

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