SystemVerilog - random testbench for a mux?

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brenox

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SystemVerilog

Hi, I'm trying to do a random coverage of a serial. For this I'm first trying to do a testbench for a mux 2:1. Actually I've already did a testbench of this, but I'm not getting it right when I try to make it random.

Does anyone know how to do a random testbench for a mux?

Thanks.
 

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