SystemVerilog Project ideas

[hannibal2469]

Hi,

I am doing a course in SystemVerilog at my university and I am searching for an idea to do my final project on, something that will teach me SystemVerilog and also something that isnt too small/simple, something that if someone looks at my resume will show that I have a good hold of the language. I will be describing the design in SystemVerilog and also verifying it in SystemVerilog.

Thanks

 

[MSBR]

IMO, SystemVerilog(SV) is more preferred for verification. Some synthesis tools, though, do support some features of SV for synthesis, but some of its more advanced constructs are not suitable for synthesis. If I were to design a project. I would have gone for the designing in Verilog and the Verification Environment in SV.

Thanks,
MSBR

 

[Taher_Selim]

Hello,
I assume that you have learnt the concept of testbench environment in System Verilog. I mean you are now aware of main testbench components like monitor, driver, stimulus generator,.... if so you need only to pick any ready design (gray counter, FIFO,..) then start creating testbench for it using System Verilog.
If your target is to use system verilog for synthesis, just pick up any ready module, and start to describe it in System Verilog, however you will need also to create testbench for it.

Regards

 

[MSBR]

I think that System Verilog is much more powerful. You can consider learning Randomization, Dynamic Memories, Classes, Programs and Assertions etc for Robust Verification. I agree that picking up a Ready-made design would reduce the designing effort from your end and will allow you to focus on the Verification only.

If you are looking for a reference then I have found Chris Spear's book named "SystemVerilog for Verification" a very helpful resource.

Hope that helps.

Thanks,
MSBR