SystemVerilog: Parameters defined with $size function...

[korgull]

system verilog parameter

Hi,
Well, now that I seemed to have solved my problem finding a conversion of the VHDL 'LENGTH command, I now have a problem with the way I want to use it.

I would like to use the $size command to define variables in a bit width. For example I thought that I could do this..

parameter XH  = ($size(X) - 1);
parameter XMU = ($size(X) / 2);
parameter XML = (($size(X) / 2) - 1);

so that I could do this:

a1 = X[XH:XMU];
a0 = X[XML:0];
b1 = Y[XH:XMU];
b0 = Y[XML:0];

Unfortunately, I cannot place the $size command in there as it tells me that I have an "Illegal operand for constant expression" Furthermore, I need to place the "parameter" code in the beginning, which isn't the most ideal place for it for what I want to do as I need my function to be recursive.

Is there a way that I can establish an equation that defines the bit width of "X" and "Y"? Or does it have to be defined with the parameter statement.

thanks

 

[boardlanguage]

systemverilog parameter

Which simulator are you using (Questasim, VCS, or Incisive)?

Some simulators don't support the full Systemverilog language.

I'm pretty sure the argument of $size() is known at compile/elaboration time. Therefore, the output of $size() inherits the constant/static property, but some simulators don't recognize this. But I might be overlooking something

For example:

parameter bit [2:0] STATE_A = 3'd0;
parameter bit [2:0] STATE_B = 3'd1;

typedef enum bit [2:0] {
  S_A = STATE_A,
  S_B = STATE_B
} te_states;

// *compile-error in Ncsim 8.1
//  "Enum values must be literal constants.  Temporary implementation limitation."

The above code fails in Ncsim 8.1, but compiles fine in Modelsim 6.3, Aldec Riviera Pro, Synopsys VCS. (Shame on Cadence...)

In the example you posted, did you try substituting the expressions "$size(X)-1" directly inside the procedural-assignment?

a1 = X[($size(X) - 1):($size(X) / 2)];

 

[korgull]

systemverilog $size

In the example you posted, did you try substituting the expressions "$size(X)-1" directly inside the procedural-assignment?

a1 = X[($size(X) - 1):($size(X) / 2)];

I'm using Cadence Analog Environment with the AMS simulator. I tried using your idea (good idea), but.. it did not work. I got the error:

a1 = X[($size(X) - 1) : ($size(X) / 2)];
---------------|
ncvlog: *E,NOTPAR (/verilog.v,18|12): Illegal operand for constant expression [4(IEEE)].