SystemVerilog Coverage iff

[davyzhu]

Hi all,

I am new to SystemVerilog.
My friend told me TYPE1 can be compiled and TYPE2 cannot be compiled, is it right?
BTW, I use cadence tools.

covergroup cg0@(negedge CLK);
   one_sig: coverpoint one_sig
        {
               //TYPE1 
               bins a = {1} iff(vaild )
               //TYPE2
               bins a = {1} iff(vaild ==2);
               ... ...
        }

Best regards,
Davy

 

[aji_vlsi]

Hi Davy,
LRM allows the Type 2 also. The following code works with VCS.

module cov_test ;
logic CLK;
logic a;
integer valid;
logic one_sig;
covergroup cg0@(negedge CLK);
    coverpoint one_sig
        {
               //TYPE1
               bins a = {1} iff(valid );
               //TYPE2
               bins a1 = {1} iff(valid ==2);
                       }
   endgroup : cg0
   endmodule : cov_test

Which version of NC did you use ?

HTH,
Ajeetha, CVC
www.noveldv.com

 

[davyzhu]

Hi Ajeetha,

Thank you!

I use nc: 05.50-p004. And I will try the code later.

Best regards,
Davy