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SystemVerilog Clocking Block assign data time?

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davyzhu

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Hi all,

I use Clocking Block to construct testbench component like driver.
And I am confused with what time Clocking Block to synchronize data.

For example, there is "sync_fifo_if_i" interface instance and "wr_driver_cb" clocking block.
The clocking block is
Code:
//-----
  clocking wr_driver_cb @ (posedge clk);
   default input #setup_time output #hold_time;
        input full,almost_full;
        output din,wr;
  endclocking : wr_driver_cb 
//-----

The data assignment sequence is
Code:
//-----
@(sync_fifo_if_i.wr_driver_cb) 
din <= data_in;
wr <= 1'b1;
@(sync_fifo_if_i.wr_driver_cb) 
//-----

The questions are
1. Will data assignment (synchronize) at the first @... or the second @...theoretically?
2. Is
Code:
@(...) din<=data_in;
and
Code:
@(...); din<=data_in;
(note the ; difference in @) difference?

Thanks!
Best regards,
Davy
 

spauls

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Davvy ,

Both will do same job.
 

Guru59

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Hi......davyzhu

i want to know abt system verilog as well it will be really great if you upload some books related to system verilog................

i have gone through asic-world.com but i want to practice the programming for it..........

thanks...........
 

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