[SOLVED] [SystemVerilog] Can not cover FSM with one hot state

[jcungduoc]

I covered FSM with enum states successfully, but when I changed into onehot, it did not cover FSM.
Please help me, here's my code.

module fsm1hot(
input reg clk, reset_n,
input reg [2:0] st,
output reg [4:0] current_st, next_st
);
parameter T = 1;
//input clk, reset_n;
//input [2:0] st;
//output reg [4:0] current_st, next_st;

//always #T clk =~ clk;
parameter
ST_A = 4'd0,
ST_B = 4'd1,
ST_C = 4'd2,
ST_D = 4'd3,
ST_E = 4'd4;

always @(*) begin
next_st = '0;
case (1'b1)
current_st[ST_A]: begin
case (st)
0: next_st[ST_A] = 1'b1;
1: next_st[ST_B] = 1'b1;
2: next_st[ST_C] = 1'b1;
default:
next_st[ST_E] = 1'b1;
endcase
end
current_st[ST_B]: begin
case (st)
0: next_st[ST_B] = 1'b1;
1: next_st[ST_C] = 1'b1;
2: next_st[ST_D] = 1'b1;
default:
next_st[ST_E] = 1'b1;
endcase
end
current_st[ST_C]: begin
case (st)
0: next_st[ST_C] = 1'b1;
1: next_st[ST_D] = 1'b1;
2: next_st[ST_A] = 1'b1;
default:
next_st[ST_E] = 1'b1;
endcase
end
current_st[ST_D]: begin
case (st)
0: next_st[ST_D] = 1'b1;
1: next_st[ST_A] = 1'b1;
2: next_st[ST_B] = 1'b1;
default:
next_st[ST_E] = 1'b1;
endcase
end
current_st[ST_E]: begin
case (st)
0, 1, 2: next_st[ST_A] = 1'b1;
default:
next_st[ST_E] = 1'b1;
endcase
end
default: begin
end
endcase
end

always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
current_st <= '0;
current_st[ST_A] <= 1'b1 ;
end
else
current_st <= next_st;
end

endmodule

Thanks in advance!