SystemC .. Generate Statement

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omara007

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Hi folks ..
Anyone knows how to do something like the ( vhdl generate statement ) in SystemC ? ..
Simply I have a module and I want to instantiate it many times in an upper level module .. how to do that ?
 

You can try somthing like this!
ff_with_pc is module of d flipflop with preset_clear and i am generating
three instances of it here...
Hope this helps!


Code: 
 ff_with_pc *lq[3];
  sc_signal<bool> qn[3], q[3];
  int i;
  char *module_name;
  SC_CTOR(upc){
    for (i=0; i<3; i++) {
       sprintf(module_name, "ff_with_pc_lq%d", i);  
       lq[i] = new ff_with_pc(module_name);
       lq[i]->clock(clk);
       lq[i]->din(qn[i]);
       lq[i]->preclr(pc);
       lq[i]->q(q[i]);
       lq[i]->notq(qn[i]);
    }
    //Destructor
  ~upc(){
    for (i=0; i<3; i++)
      delete lq[i];
}
 

However, this example is not synthesizable into hardware.
Works fine for behavioral model, I tried it in catapultC and get into troubles.

Wonder if there is an easy way to create a systolic array as in VHDL.
 

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