system verilog & verilog

[alieeldin]

hi
i want to know the differance between verilog and system verilog
what mean 'X' in system verilog
--
alie eldin

 

[vivek]

system verilog is basically accellera's extension for of verilog 2001. It has all the older verilog capabilities with some new features. it also has the verification specific capabilities borrowed from open vera.

'X' in system verilog is same as in verilog. It means in determinate or unknown value. When conflicting values are driven by multiple sources to an output or inout port, it results in X. In real world X does not exist.

 

[kachuisa]

about "H","L","_",... in VHDL?