System Verilog rtl question . . . ! ! !

[vizpal]

Hi, I am working on a SV verification project. I want to access some internal rtl signals in my Testbench. How is this done ???

I came across "$root" in SV, but am not sure how to use it !!!

Can anybody explain me how this can be done...

If possible give examples...

Thanks in advance !!!!

 

[aji_vlsi]

Just like plain Verilog - use a.b.c.d

Ajeetha, CVC
www.noveldv.com

 

[veeramuthuece]

if you wanted to access some variables inside the RTL from testbencs.
you have to do hireracial reference like
tb.dut.internalblock.signal

 

[vizpal]

Can we define this as part of interface file ???? :idea:

 

[vpk]

mybe by adding testpoints...

 

[shobhitk]

Use hireracial names of signals

Top_Level.mid_Level.lower_level.Signal_name

 

[xuanzhu]

but this is a very bad simulation style, because if the design has been synthesised, some signals will vanish, and you have to modify your testbench. The best way is to regard your design as a blackbox, and insert some properties and assertions in your rtl code to help you debug