dipin
Full Member level 4
hi,
i am verifying a design using system verilog test bench.
input to the design are being randamized. my input is 16 bit width.
in_data <= $urandom_range(1000,9000);
in this ,is there any way to know how much %(percentage) of input is given to the design ???
in between 1000 and 9000 how many inputs are given to the design
( in %) . if anybody know please help
thanks & regards
i am verifying a design using system verilog test bench.
input to the design are being randamized. my input is 16 bit width.
in_data <= $urandom_range(1000,9000);
in this ,is there any way to know how much %(percentage) of input is given to the design ???
in between 1000 and 9000 how many inputs are given to the design
( in %) . if anybody know please help
thanks & regards