using the following example arrays:
Code Verilog - [expand] |
1
2
3
| logic [3:0] bt1[7:0];
logic [3:0][7:0] bt2;
logic [7:0][3:0] bt3; |
The bit definitions of the arrays are:
Code:
bt1 (8 unpacked nibbles):
7777
6666
5555
4444
3333
2222
1111
0000
bt2 (4 packed bytes):
33333333222222221111111100000000
bt3 (8 packed nibbles):
77776666555544443333222211110000
where the number represents the number of the nibble (the bit vector).
As you defined your slice as:
Translating to a range that is valid for the example we could attempt a slice like this:
This results in the following bold red bits being sliced in each case:
Code:
bt1:
7777
6666
5555
4444
33[b][COLOR="#FF0000"]3[/COLOR][/b]3
22[b][COLOR="#FF0000"]2[/COLOR][/b]2
1111
0000
bt2:
333333[b][COLOR="#FF0000"]3[/COLOR][/b]3222222[b][COLOR="#FF0000"]2[/COLOR][/b]21111111100000000
bt3:
777766665555444433[b][COLOR="#FF0000"]3[/COLOR][/b]322[b][COLOR="#FF0000"]2[/COLOR][/b]211110000
all of these slices are illegal as they are not contiguous bits (packed), hence the syntax error you recieve, even when you use ranges that are valid for either of the array dimensions.
Verilog/Systemverilog requires that the packed bit-vector slice is the right most bracketed range all other dimensions have to be single number indices.