[SOLVED] System Verilog conditional parameter

[shparekh]

Hi,

I have a following statement in my code -

genvar sliteIfIter_grp1
generate for (  sliteIfIter_grp1=0;
                  sliteIfIter_grp1<MAX_SLITE_GRP1;
                  sliteIfIter_grp1+=1)

The psuedo code to assign MAX_SLITE_GRP1 is

 if (SLITE_NUM > 4)
   localparam MAX_SLITE_GRP1 = 4
 else
   localparam MAX_SLITE_GRP1 = SLITE_NUM

SLITE_NUM is a parameter which can be overridden at the time instantiating the block.

Can you please suggest how I can write this in system verilog?

Thanks.
Best regards,
SP

 

[dave_59]

localparam MAX_SLITE_GRP1 = (SLITE_NUM>4)? 4 : SLITE_NUM;

and the same generate block, or

genvar sliteIfIter_grp1;
for (  sliteIfIter_grp1=0;
                  sliteIfIter_grp1<( (SLITE_NUM>4)? 4 : SLITE_NUM);
                  sliteIfIter_grp1++)

 

[shparekh]

Super. I knew there had to be a way.
Thx.