SYSTEM GENERATOR and VERILOG HDL

[hassantalal785]

HI . kindly some one tell me : how to integrate VERILOG written code and XILINX SYSTEM GENERATOR design together for FPGA implemenation.

means that i have some part of my complete system, designed in XILINX SYSTEM GENERATOR and some part i have written in VERILOG .. so Can i make a SYSTEM GENERATOR block from my VERILOG CODE ?

OR HOW can i integrate my both designs in ONE.... ?

thanx