System C & system Verilog

[mssajwan]

for learning system Verilog
1. http://www.veritools.com/industry_solutions/overview.html
2. http://www.doulos.com/knowhow/sysverilog/tutorial/
for learning system C
1. http://www.forteds.com/systemc/index.asp

 

[rakesh_aadhimoolam]

https://www.asic-world.com/systemverilog/index.html

is also a good place

 

[matthew_wang]

what is the difference between the SystemC and System Verilog? thanks

 

[mssajwan]

Hi,
system C and System Verilog both are system level modellinbg language.
stating much of the differnce is difficult as it will vary.
both are mainly used for verification at SOC level.
system C is good in modelling computational models,while system verilog is close to verilog( system verilog is superset of verilog)

both have C++ fatures.
now its upto the user to make use of them

 

[sumit_techkgp]

SystemC is full fledged OOP Language while SysteVerilog not. SystemVerilog is good for RTL design and modelling. SystemC is good for harwdware-software co-simulation

 

[lovou]

I am a beginner in SystemVerilog, could you recommend me 1 or 2 handy book to learn it?

I have the Hardware design experience and VHDL knowledge, want to start to learn more about Verilog HDL.

 

[krishna_1980]

systemverilog for verification by chris spear and ieee manual (it is available in edaboard) are good material for beginers

 

[darylz]

both are good...
but looks like SV is for verification and SC is for system modeling...
My question is: Can I simulation my model by SC in SV test env?

 

[neoflash]

anyone could suggest good web sites, with good example codes, for prime C on system level simulation?

 

[polu]

As per my knowledge systemC is a language with only models..it will not appeal anything that can be realized as a hardware...Where as System verilog is for both hardware realization and it's functional verification.