systemc vs systemverilog
Don't forget e/Specman!
The answer is: it depends.
If you are coming from a software backgorund and you want to write a behavioural system model, then SystemC is probably best. SystemC RTL is however horrible, ugly, verbose and unreadable, and you'd bve better using SystemVerilog, in my opinion. It is, however, possible
Vera is a verification langauge only. It also has the disadvantages of being proprietary to one vendor (despite openvera) and cannot be used for RTL, so you always need 2 languages. Also, Synopsys seem to be pushing SystemVerilog more and have incorporated much of the vera functionality into SV anyway. e is a simialr story but with s/Synopsys/Cadence/
SystemVerilog can do it all. It can do RTL well, is great for verilog engineers as it is backwards compatible, and has lots of OO and verification features that make it as good or better than SystemC or Vera for behavioural and verification. However, support for it is still ramping up and not all vendors fully support it yet, and those that do will no doubt have some bugs in their implementations, especially as the official standard for it is not even published yet!
You'll aslo find, however, that you need to pay extra for all these solutions. There is a free SystemC compiler, but it gives poor performance compares to those compilers included in commercial products.