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I don't think that system c is really better then a hadl like VHDL or Verilog! I think there is only one risem why to change to system c. There are only ~10000 VHDL Programmer and ~1000000 C Programmer!
I think SystemC has only reason for existence to help software engineers with hardware/software co-design. However their main problem is lack of knowledge of the underlying micro-archtiectures and not the need for another language.
I don;t think that SystemC will ever gain as much acceptance as VHDL/Verilog (hardware) and C/C++ (software) do. For the next 10 years, the two worlds will not come together.
vhdl and verilog are standardized by ieee. also they are older than systemc and about all programs supports these two hdls, but not systemc. vhdl and verilog (i prefer vhdl) is more popular than systemc and their codes are portable because of wide range of sotware. i think they are better than systemc.
amir
Man and woman are different, none is better than the other
SystemC is for high level modeling, Synopsys is giving up behavior synthesize. However, new SystemC will include RTOS and move up one notch. System Verlog will bridge the gap for behavior description and varification.
I think SystemC has only reason for existence to help software engineers with hardware/software co-design. However their main problem is lack of knowledge of the underlying micro-archtiectures and not the need for another language.
I don;t think that SystemC will ever gain as much acceptance as VHDL/Verilog (hardware) and C/C++ (software) do. For the next 10 years, the two worlds will not come together.
I agree the_penetrator's point.
SystemC can help system analyzer to determine which architecture is suitable and help software engineers develop their applications earlier.
V*HDL has poor compile option.
especially VHDL.
and so on VHDL coding is very^10 redundancy.
Don't u feel pain in writing VHDL codes, if u know C/C++ programming languages.?
i think
SpecC/SystemC makes the progress of electric resercher/engineer's works(between making algorithm and FPGA/ASIC design) seamless
and increase productivity.
system c is a hdl even if it tries to pass itself off as C. It might be based on c, written in c, and use c syntax, but it is not a high level language. It is certainly not as readable as c. you still need to describe things on an rtl level, to get hardware. and there is a steep learning curve to do anything interesting. Where it does have its strengths is simulation and verification, and HW/SW co-design.. and the fact is there is a real drive to be able to to be able to describe hardware in c because as a previous writer said, there are a lot more c programmers than hdl programmers. but my argument is , from the little experience i have, VHDL or Verilog, are much better at describing hardware and are much easier to learn than systemC, if you have never done much C. don't think you are going to be programming in c cause it don't look nothing like the real thing.
p
some "silly" positive feedback due to reasons like the existence of over 1,000,000 C programmers and much less VHDL programmers may give the undeserved the stand int\ the first place and deny the the deserved from the best.
In my view I think there is a best language to talk to every individual and there is a best HDL language (either instruction oriented or cell oriented) to describe every circuit
systemc is the language for system design and defined as system description language (SDL). vhdl/verilog is the language for hardware design and defined as hardware description language (HDL). we can't say which is better than which and ignore the others that are disadvantage. instead, they are complement to obtain the higher level of design methodology.
In my view, SystemC probably is good for high level modeling, but it is dump for RTL level.
Take a look at the synopsys's "Describing Systhesizable RTL in SystemC",
and you may not want to use systemC as your HW design language.
Don't compare SystemC to HDL's .. simply because SystemC is system-level modeling language while others are for hardware description .. for the time being one can't compensate the other .. u better think of SystemC and other HDL's as complementing each others .. or that SystemC is a good step towords having no problems in HW/SW co-design.
Keep in mind that System is not yet mature from the point of Synthesis .. for that it can't beat other very mature HDL's like VHDL and Verilog ..
System C is good yes it is good but VHDL is also good...see actually its relative.
Depends not on the person using it but on the task at hand...system C is very good for efficient verification but its not very convenient to use...as not many hardware programmers like to uuse C...so there are many prons and cons...but there is time before any one takes a higher position ... right now tVerilog/VHDL/sysetm C and yes OVA will co-exist
yeah right... and Kirsten Dunst is better than Anna Paquin...
look here friends, there is no such thing as a better language! It depends on what you want to do.
For example:
Kirsten is more attractive, her characters are emotionative but can also give you that unique ice-cold look. See can play chillingly well bad-behaved adolescents (a very few years ago), e.g. as in "Interview with a Vampire".
Anna has a little more depth in her roles, her characters are not very sexually-minded, is also more warm (even as Rogue!). She has also acquired the little tin man at the age of 11.
So to the point, SystemC is for platform tuning, system-level design playing with the size of memories, at accessing peripherals and accelerators e.g. at the transaction-level.
HDLs are simulation/then-turned-synthesis languages that will dominated the synthesis task for 10 more years. SystemC will not compile that good for some time more.
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