BartlebyScrivener
Member level 5
I have a design which is to be integrated into other designs on an FPGA. I would like to see how it performs in isolation (clock speed/size etc). If I try to synthesise, obviously as no inputs/outputs are assigned, vivado just clears all the logic as it does nothing. How can I get vivado to pretend there might be inputs without assigning all my i/o to pins?
I hope that makes sense!
Thanks.
I hope that makes sense!
Thanks.