Synthesizing Design : Working with Libraries

[nitint08]

Hi

For Synthesizing a RTL to netlist using either Synopsys DC or Cadence RC, we need
Technology libraries => which has cell complete information.
Symbol Libraries => cell schematic information
Constraints File => various delays, clock definitions specified.

Please tell how does these Tech and Symbol files being generated.
To me, these library are developed by Backend people (basically Library development team). They develop the layout using layout-editor and analyze the cell parasitics using tool and the output is
generated as file called technology file and symbol library.

Now these are given to Compiler which uses constraints and map the library cells to the RTL blocks and come up with the file where RTL information has been transformed into cells level information
having delays incorporated.

Please put your thoughts and correct my perception if wrong.

Nitint08

 

[YuLongHuang]

HI~!

In my company, this macro/library file is also generated by back-end team.
To develop an IP, we just write a RTL and later synthesize.
After that, we just give our netlist to the back-end team and they will give us corresponding library file.

I think there is nothing wrong in this flow.
Layout must be done in advanced such that the input capacitance/output driving ..etc can be determined.
Different layout may cause different parasitic.

The above I talking about is meant hard macro.
I have never used soft macro until now.

 

[nitint08]

Your opinion is in sync with what i have described.

Infact what i feel the library development go hand-to-hand in parallel with IP development.
Library development people test there cells by incorporating them in some testchip which is again check by them(library development guys) on silicon. Once done they sign-off the libraries to get used at GLS.