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Synthesizable Operators in VHDL

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ravics

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Which of the following operators are NOT synthesizable by Synthesis tools?

*
+
-
&
 

TrickyDicky

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They are all synthesisable for the correct types.
 

ravics

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Got this question in a competitive exam so if there is a correct ans what it would be, like closest one?
 

TrickyDicky

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what a terrible question. Probably relates to synthesis 10-20 years ago.

---------- Post added at 10:55 ---------- Previous post was at 10:50 ----------

It is probably asking for *, but its been fine to use * for at least the last 6 years (since Ive been coding).
And Ive seen code going back 10 years that uses *.

+ and - are basically the same, an adder
& is just concatenate.
 

ravics

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what a terrible question. Probably relates to synthesis 10-20 years ago.

haha.. thats what I thought when I saw the question.
 

the_penetrator

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Hi

really bad question. Some old-fart, zero-knowledge examiner/interviewer must have thought about it.

Now to the point:
Probably the non-synth op is the multiply "*". Most tools back then didn't provide module generators for synthesizing the operation.
Also the "&" operator (concatenation) is certainly synthesizable, since it means (for the correct types, of course) grouping of signals/wires.

In what country did you have the interview? This question shows what jerk-off company this interviewer works in.

the_penetrator

---------- Post added at 23:50 ---------- Previous post was at 23:46 ----------

Also another point.

Since July 2000 that i made it to this business as a worker, I never had to do a single interview. I did a couple of "technical presentations" but never a strict interview.
I used to just sat down with those guys and present some tidbits of my portfolio (starting from my univ. years, still growing, much more mature now). Nothing more was required to get the job.

It is important to have a good portfolio and processes that automate your day-by-day work. Otherwise you will be victimized by such low-life fat-ass examiners.

More on this, on some other day.

Kind regards
the_penetrator
 

kmdineshece

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I think so.............

"&" operator can't be sysnthesized by VHDL synthesis tool!............
 

ads-ee

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I think so.............

"&" operator can't be sysnthesized by VHDL synthesis tool!............
I started using VHDL in '95 and every tool I worked with supported &.

What is your supporting evidence that synthesis tools don't support it? Perhaps it's your expertise in analog and micros that gives you such indepth knowledge of VHDL.
 

TrickyDicky

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Who'd have thought concatenating two busses would be such a hard thing for a synthesisor to do.
 

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