synthesizable delay using vhdl

[ravi33811]

hi can any tell how to writ vhdlcode
to introduce delay which is synthesizable

like
a<=b after 50 ns;
c<= d after 30 ns;

 

[avimit]

delays are not synthesizeable.
The only option is, to set up a counter which delays the signal by a known 'count' the frequency at which counter works, and the count will determine the delay
Kr,
Avi
http://www.vlsiip.com

 

[master_picengineer]

Hi,
Synthesizable delay can be obtained by using dff. In your case you also need ounter like mensionned by Avi.
Cheers,
Master_picengineer

 

[gck]

Counter is the best idea for introducing delay in the circuit. But Count has to be calculated according to operating frequency.

 

[vlsi_freak]

There is no standard synthesizable delay in VHDL.
You can go for some divide by counters. If you know the clock frequency find a suatable count to so that you get that delay.

a <= b after 50 ns, is not a synthesizable construct.

 

[Thinkie]

For small delays, (not 50ns) you can also pass the desired delay as synthesis parameter in Synopsys.

Your synthesised circuit will insert some buffers to form the asked delay and this can be passed on the SDC on your back-end tool.