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SYNTHESIZABLE AND NON SYNTHESIZABLE STATEMENTS IN VHDL ?

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hemant2007

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what is mean by SYNTHESIZABLE AND NON SYNTHESIZABLE STATEMENTS (VHDL )?

give examples?

thanks in advance!
 

ehsanelahimirza

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synthesizable are those which will generate some hardware when implemented

and non-synthesizable are those which dont generate any kind of hardware, they are just the instructions for the compiler/assembler

any good example not in mind at the moment sorry 4 that
 

echo47

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Non-synthesizable can also mean the compiler could convert the HDL into hardware, but for some reason it doesn't do it, usually because it requires too much effort, or the target hardware doesn't adequately support it. Common examples are floating-point arithmetic and precise time delays.
 

gck

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The statement which directly can be used to generate the Hardware called as Synthesizable statments.

The statements which can't make any hardware is known as Non-synthesizable.
Ex: wait, after statements.

They can not generate any hardware. See for generating delay we have counter. So 'wait' as such will not do anything. As far simulation is concern it will show you same output but after synthesis it will not.

Please correct if I am wrong anywhere.
 

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