synthesizable 2-dimentional generic array in vhdl

[meliT]

Dear all,
Hi.
I've got a problem synthesizing the generic mux code with
Design Compiler. As I know, it is not possible to vhdl synthesize a
2-dimentinal array with generic parameters in DC. So, I thought of
defining a new type like "wire" which is an array of std_logic_vector.
Some colleagues told me this type might be synthesizable. But I have
problem defining the new type with constant variables.
The code follows is my vhdl code for it. Is it not really possible to define an array
type with parameters?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------
--------------------------
package type_def_pack is
  
  constant s is integer range 1 to 5 := 1;
  constant line_width is integer range 0 to 31 := 8;
  type wire is array (0 to 2**s -1) of std_logic_vector(line_width-1 downto 0);
  
end package;  
  
--------------------------
--------------------------

entity Generic_Mux is 

  generic ( line_width : integer := 8);
  port ( Dinput : in wire;
         sel : in std_logic_vector (s-1 downto 0);
         output : out std_logic_vector(line_width-1 downto 0));
end Generic_Mux;

-------------------------
-------------------------
architecture behavioral of Generic_Mux is
BEGIN
      output <= Dinput(conv_integer(sel))(line_width-1 downto 0);
	
END architecture behavioral;

 

[rca]

You could synthesis a multiple array dimension.
One of both dimension need to be fix.

TYPE t_STD_LOGIC_VECTOR_1_DOWNTO_0_VECTOR IS ARRAY (NATURAL range <>) of STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL toto : t_STD_LOGIC_VECTOR_1_DOWNTO_0_VECTOR( 3 DOWNTO 0); -- array of  [3:0][1:0]

or

TYPE  t_tata IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(c_width-1 DOWNTO 0);
SIGNAL tata : t_tata; -- array of [3:0][c_width-1:0

]

 

[FvM]

The code has several syntax errors, but not related to the type definition as such.

The part to be corrected:

 package type_def_pack is
  
  constant s :integer range 1 to 5 := 1; -- originally wrong constant syntax. The range specification is meaningless, but doesn't actually hurt.
  constant line_width :integer range 0 to 31 := 8; -- dito
  type wire is array (0 to 2**s -1) of std_logic_vector(line_width-1 downto 0);
  
end package;  

-- the below library specification is required  for the entity
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
use work.type_def_pack.all;

entity Generic_Mux is

 

[meliT]

You could synthesis a multiple array dimension.
One of both dimension need to be fix.

TYPE t_STD_LOGIC_VECTOR_1_DOWNTO_0_VECTOR IS ARRAY (NATURAL range <>) of STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL toto : t_STD_LOGIC_VECTOR_1_DOWNTO_0_VECTOR( 3 DOWNTO 0); -- array of  [3:0][1:0]

or

TYPE  t_tata IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(c_width-1 DOWNTO 0);
SIGNAL tata : t_tata; -- array of [3:0][c_width-1:0

]

Thank u, rca. Yeh, I knew that the array can be defined with constants and fixed values for sizing. I was not sure about the generic values, and u assured me.
Thanks for your time.

- - - Updated - - -

The code has several syntax errors, but not related to the type definition as such.

The part to be corrected:

 package type_def_pack is
  
  constant s :integer range 1 to 5 := 1; -- originally wrong constant syntax. The range specification is meaningless, but doesn't actually hurt.
  constant line_width :integer range 0 to 31 := 8; -- dito
  type wire is array (0 to 2**s -1) of std_logic_vector(line_width-1 downto 0);
  
end package;  

-- the below library specification is required  for the entity
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
use work.type_def_pack.all;

entity Generic_Mux is

Thank u, FvM. Your comments does really help. I had added

 use work.type_def_pack.all;

but not the previous line, so an error occured and I omitted the line.
Thank u for your time and comments.