Synthesizability of a code

[fragnen]

Is the following code synthesizable? If not, why? Here f(sig_a) if a logical function of sig_a and g(sig_b) is another logical function of sig_b. Here sig_a and sig_b are either wire or reg.

always (posedge sig_a or sig_b or negedge reset)
if (!reset)
out<=1'b0;
else if (enable1)
out<=f(sig_a);
else if (enable2)
out<=g(sig_b);

 

[barry]

Not synthesizable because you’re missing an “@“.

but why dont you just try and synthesize it; that would be more educational than somebody just telling you.

 

[danadakk]

Being a newbee I would be fishing around for where the "@" goes....something like this

always @(posedge Clk or negedge Reset) or

always @(posedge Clk or negedge Reset) begin
.
.
.
end


Regards, Dana

 

[barry]

Being a newbee I would be fishing around for where the "@" goes....something like this

always @(posedge Clk or negedge Reset) or

always @(posedge Clk or negedge Reset) begin
.
.
.
end


Regards, Dana

There’s no ”fishing around“ required. There are tons and tons and tons and tons and tons and tons of information on the internet and in bookstores and in libraries about verilog. If you don’t even know the most absolutely fundamental aspects of it, I suggest you start by reading something.

 

[danadakk]

There’s no ”fishing around“ required. There are tons and tons and tons and tons and tons and tons of information on the internet and in bookstores and in libraries about verilog. If you don’t even know the most absolutely fundamental aspects of it, I suggest you start by reading something.

Thanks, quite aware of that, been doing youtube videos and some basic Verilog. I have
been programming since 1970 and have many languages rattling around in my head so
always classify myself as a newbee.

My comment to OP was more in case he was newcomer and thought an answer
to his question with example might help.

Regards, Dana.

 

[FvM]

The Verilog language specification doesn't enclose specific synthesis rules. Synthesizability of a Verilog description depends on hardware properties. Respectively you'd ask if the code is synthesizable for a specific FPGA family or ASIC library.

To understand, if the post#1 code snippet can be meaningful Verilog, we need to see the definition of included functions. The already mentioned syntax error has to be corrected of course.

At first sight, I don't recognize meaningful Verilog.

 

[ads-ee]

Is the following code synthesizable? If not, why? Here f(sig_a) if a logical function of sig_a and g(sig_b) is another logical function of sig_b. Here sig_a and sig_b are either wire or reg.

always (posedge sig_a or sig_b or negedge reset)
if (!reset)
out<=1'b0;
else if (enable1)
out<=f(sig_a);
else if (enable2)
out<=g(sig_b);

I don't think this code is synthesizable as the code does not match any kind of synchronous or asynchronous coding template that a synthesizer would recognize.

always @(posedge sig_a or sig_b or negedge reset)

an always block that contains posedge xxxx is used to describe a FF the additional negedge/posedge signal that follows will implement an asynchronous set/reset when used in an if statement. The additional sig_b does not match any description of a FF and will probably cause the synthesis to fail.

Besides this the sig_a is used as a combinational input to a function, which is not going to synthesize a FF.

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Code Verilog - [expand]
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// FF
always @(posedge clk)
 
// FF with async reset
always @(posedge clk or negedge reset)
  if (!reset)
  else
 
// FF with sync reset
always @(posedge clk)
  if (!reset)
  else
 
// combitnational logic
always @(*)

---