Synthesising Problem using Leonardo

[salamander]

Hi,
I'm a student and developed a quite simple serial interface using verilog.

Now I would like to Synthesise the code to flash it into an fpga, but I fails all the time with the error: "a gnd net is driven by primitive gate(s)", although it works quite well in the simulator (Modelsim).
Maybe you can help me to find the mistake (I really tried a long time)

My work can be found here: https://doorbreak.etowns.net/icd2/verilog.zip

thanks a lot for your help and maybe you can also tell me what else I could do a better way

salamander

 

[khorram]

In line 60 of vdirect_transceiver.v, you should assign "0" to the "next_bit_counter" not "bit_counter". I think the "byte_to_transceiver" input is never used, so the synthesis tool connects it to the GND.

Regards,
KH