Synthesisable Mod operation in VHDL

[ayush15]

I am trying to write a synthesisable VHDL code for the mod operation in VHDL. Since the mod operation is not synthesisable for operands other than powers of 2, a separate code needs to be written. I want to perform mod operation on a 8-bit number by 5. I have tried the code below but this does not work.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity modop is
port(x: in std_logic_vector(7 downto 0);
	r:out integer
	);
end modop;

architecture Behavioral of modop is
begin
process(x)
variable s1,s2: integer:= 0;
variable n,s3: integer:= 1;
begin
s1:= to_integer(unsigned(x));
while s3>0 loop

s2:= 5*n;
s3:= s1-s2;
if s3=0 then
r<=0;
elsif s3<0 then
r<= s3+5;
elsif s3>0 then
n:=n+1;
end if;
end loop;
end process;
end Behavioral;

I have also tried the code below but this too doesn't works.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity modop is
port(x: in std_logic_vector(7 downto 0);
	r:out unsigned(7 downto 0)
	);
end modop;

architecture Behavioral of modop is
signal s4:unsigned(7 downto 0):= "11111011";
signal s5: unsigned(7 downto 0):= "00000101";
begin
process(x)
variable s1,s2:unsigned(7 downto 0):="00000000";
variable s3: integer:= 1;
begin
s1:= unsigned(x);
while s3>0 loop
s2:= s1+s4;
s3:= to_integer(s2);
end loop;
r<= s2+s5;
end process;
end Behavioral;

Please help me regarding this mod operation.

 

[TrickyDicky]

the problem will be because you're using a while loop. Because the synthesisor doesnt know how many iterations of the loop are required, it has to consider worst case, and as s3 is an integer, it needs to make it 32 bits (and hence could take a huge number of iterations to iterate down from s3=2^31. ). Loops need to be unrolled into a big long chain of firmware.

So, moral of the story - avoid the mod operator. Also avoid while loops.

Think about the hardware you need, not the code you need to write. Draw a circuit diagram for your operation before writing the code. After all, VHDL is a description language, not a programming language. If you dont know what you're describing, you cant write the code.

 

[FvM]

The mod operation is synthesizable by most tools, but it infers a parallel divider to get the remainder which is often unwanted. A while loop in contrast isn't synthesizable.

The best solution depends on your design requirements. The parallel divider may be suitable for small numbers like 8-bit, if you want to minimize the resource count, a serial divider can be an alternative, also a look-up table.

 

[ayush15]

@TrickyDicky: Thanks for your reply. I would not use use while loop anymore. Actually, I need to perform mod addition. So, after doing addition of two 8-bit numbers, I need to take the modulus of the sum with 5. Could you please help me in describing this operation through a circuit or something which I could use to write a VHDL code.

- - - Updated - - -

@FvM: Thanks for your reply. I don't know anything about parallel or serial dividers. Could you please give me some links from where I could study about them and learn how to use them. Also, I think an LUT would be a tedious job to do.

 

[TrickyDicky]

Both Altera and Xilinx provide divider cores that are fully pipelined. You need to read up on the appropriate one for your technology.
a LUT can be done with a constant in VHDL, that can easily be initialised with a function in VHDL.

 

[FvM]

A non-pipelined 8-bit divider still runs at > 50 MHz between registers with slowest Cyclone III speed grade, without register retiming.

if rising_edge(clk) then
sum <= a + b;
c <= (sum mod 5);
end if;

 

[ayush15]

FvM: I am using Xilinx Project Navigator for simulation and Xilinx synthesis tool for synthesising my code. I am not using any thing of Altera.

 

[mrflibble]

FvM: I am using Xilinx Project Navigator for simulation and Xilinx synthesis tool for synthesising my code. I am not using any thing of Altera.

Good thing then that xilinx offers divider cores as well. Just fire up coregen, and pointey clickey it together. For bonus points you can read the fine pdf document about that core by pressing Ye Olde Documentation Button (in coregen).

 

[TrickyDicky]

FvM: I am using Xilinx Project Navigator for simulation and Xilinx synthesis tool for synthesising my code. I am not using any thing of Altera.

It doesnt really matter - bother altera and xilinx have similar devices, so results should be pretty similar.