I'm sorry, I don't totally understand why using a nand2 as an inverter is not possible in your technology. Or you could use some other cell to serve the inverter funtion. You said (A+B') is available. All you would need to do is create a copy of that cell with the A term tied to logical low, then change the description in the .lib file so that the output pin function : "!B" ;. Technically it is still a (A+B') gate. What am I missing? Could you explain the problem a little more?Hey all. Thanks for all your ideas. I cannot write here all the technology details, but it is somewhat domino-logic like. Meaning, that each cell is actually constructed with 2 smaller cells. Therefore i can creat a nand-inv chain, but cannot inv itself as a lone cell. Regarding trav1s post, we have other logic alternatives in our library for the inverter and don't need to worry about our IC's delay and power consumption (which are much better than in standard CMOS technology).
Solution 1: We already tried it, putting an "infinite" delay and power to a dummy inverter cell in hope the the synthesizer will not use it. But in fact, some inverters are still remain after the synthesis proccess.
Solutions 2+3: As I mentioned before, an inverter implementation using nand2 with the legs connected is not possible in our technology, so it is not relevant.
If you still have some creative ideas, we would very like to hear them.
Thanks again...
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