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[Synthesis] Why not to over-constrain clock periods and in/out delays? No WLM synthes

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ivlsi

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Hi there,

Let's say we have a bad WLM. So, why not to use Zero-WLM and over-constrain the clock periods and in/out delays?

How the design might be synthesized without WLM? Is it difficult to prepare Zero-WLM by yourself or it always should be provided by the vendor?

Thank you
 

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