Synthesis using Synopsis Design Compilor

[digiworld]

Dear All
I have a verilog RTL model. I want to synthesise my model using design compilor. Would anyone tell me ho should i proceed if i want my vdd to 0.6 or so using 130nm tech.

Thanks in advance.

 

[ljxpjpjljx]

you use smic or tsmc lib?

 

[vlsichipdesigner]

hi,

my 2cents,

* You need to have libraries
* you need to have design constraints

to better understand the flow of syntehsis visit
https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/asicsynthesisflow.html

https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/synopsysconstraints.html

myprayers,
chip design made easy
https://www.vlsichipdesign.com

 

[vimedu]

I use umc 130 tech libraries. I am able to set operating conditions as well. But concern is that How will I synthesize my design and measure power at say 0.4(volt)?